The present invention relates to a masking process.
A thin film transistor liquid crystal display (TFT LCD), which has the advantage of small volume, low power consumption, and substantial no radiation, has become a mainstream of the present flat panel displays. A TFT LCD panel is formed by assembling a color filter substrate and a TFT array substrate opposing each other with a liquid crystal layer interposed therebetween. An array substrate typically is manufactured through a commonly used five-mask (5Mask) or a four-mask (4Mask) process. In the process for manufacturing an array substrate, the steps of film depositing, photolithography processing using a mask (photo mask), and etching are performed repeatedly for several times. Taking a five-mask process as an example, there are five steps, each of which includes photolithography using one mask. The five steps include those for forming a gate electrode and a gate line, forming a gate insulating layer and amorphous silicon semiconductor layer, forming a source/drain electrode and a data line, forming a passivation protection layer, and forming a pixel electrode, on a substrate.
Currently, a conventional photolithography process includes coating a photoresist, pre-baking, exposing with a mask, developing, and post-baking, and these steps have great influence on forming of a pattern on a TFT-LCD array substrate. Coating a photoresist is to coat a photoresist on a substrate on which a film is formed by a previous process. Pre-baking is to pre-heat the photoresist and remove the water from the photoresist to increase the adhesion between the photoresist and the substrate. Exposing is to irradiate light such as UV light through a mask onto a certain portion of the photoresist. Developing is, for example, to remove the portion of the photoresist that is exposed by using a developer so as to form a required pattern. Post-baking is, for example, to cure the unexposed photoresist in the pattern and meanwhile to increase the adhesion with the substrate, so as to avoid a phenomenon of over-etching when performing etching in the subsequent process and ensure the integrity of the pattern.
A conventional mask, for example, is to form a substantial fine pattern on a substrate, so that a portion of the photoresist is exposed where UV light passes through the mask when UV light source is irradiated. Next, for example, the exposed photoresist is removed in development to form a desired pattern. The mask pattern on a mask plate includes a transparent part, a translucent part, a hole-shape structure and/or the like.
FIGS. 1a-5b are section views illustrating photolithography procedures in manufacturing of an array substrate using a conventional technology.
FIG. 1a is a section view illustrating exposure using a first mask in a conventional process. FIG. 1b is a section view after developing using the first mask in a conventional process. FIG. 2a is a section view illustrating exposure using a second mask in a conventional process. FIG. 2b is a section view after developing using the second mask in a conventional process. FIG. 3a is a section view illustrating exposure using a third mask in a conventional process. FIG. 3b is a section view after developing using the third mask in a conventional process. FIG. 4a is a section view illustrating exposure using a fourth mask in a conventional process. FIG. 4b is a section view after developing using the fourth mask in a conventional process. FIG. 5a is a section view for exposure using a fifth mask in a conventional process. FIG. 5b is a section view after developing using the fifth mask in a conventional process. A specific workflow of the illustrated conventional process is described below by example.
In the first masking process of FIGS. 1a and 1b, a layer of metal thin film 11 is first deposited on a substrate 1, followed by coating a layer of photoresist 210 on the metal thin film 11. After pre-baking, the photoresist 210 is exposed to UV light 30 through a first mask plate 21 (as shown in FIG. 1a), so that an exposed portion 211 and an unexposed portion 212 of the photoresist 210 are formed. After developing, only a pattern of the unexposed portion 212 of the photoresist is left on the position of a gate electrode and a gate line (as shown in FIG. 1b). Next, the gate electrode and gate line are formed through post-baking, etching, and photoresist lifting-off.
In the second masking process of FIGS. 2a and 2b, a gate insulating film 12 and an amorphous silicon semiconductor film 13 are sequentially deposited on the substrate 1 after the first masking process. Then a layer of photoresist 220 is coated on the amorphous silicon semiconductor film 13. After pre-baking, the photoresist 220 is exposed to UV light 30 through a second mask plate 22 (as shown in FIG. 2a), so that an exposed portion 221 and an unexposed portion 222 of the photoresist 220 are formed. After developing, only a pattern of the unexposed portion 222 of the photoresist is left on the position of an active layer (as shown in FIG. 2b). Next, a gate insulating layer and the active layer are formed through post-baking, etching, and photoresist lifting-off.
In the third masking process of FIGS. 3a and 3b, a layer of metal thin film 14 is deposited on the substrate 1 after the second masking process, followed by coating a layer of photoresist 230 on the metal thin film 14. After pre-baking, the photoresist 230 is exposed to UV light 30 through a third mask plate 23 (as shown in FIG. 3a), so that an exposed portion 231 and an unexposed portion 232 of the photoresist 230 are formed. After developing, only a pattern of the unexposed portion 232 of the photoresist is left on the positions of a source and drain electrode layer (as shown in FIG. 3b). Next, a source and drain electrode layer is formed through post-baking, etching, and photoresist lifting-off.
In the fourth masking process of FIGS. 4a and 4b, a layer of passivation film 15 is deposited on the substrate 1 after the third masking process, followed by coating a layer of photoresist 240 on the passivation film 15. After pre-baking, the photoresist 240 is exposed to UV light 30 through a fourth mask plate 24 (as shown in FIG. 4a), so that an exposed portion 241 and an unexposed portion 242 of the photoresist 240 are formed. After developing, only a pattern of the unexposed portion 242 of the photoresist is left on the passivation layer except for the position for a via hole (as shown in FIG. 4b). Next, the via hole in the passivation layer is formed through post-baking, etching, and photoresist lifting-off.
In the fifth masking process of FIGS. 5a and 5b, a layer of transparent pixel electrode film 16 is deposited on the substrate 1 after the fourth masking process, followed by coating a layer of photoresist 250 on the transparent pixel electrode film 16. After pre-baking, the photoresist 250 is exposed to UV light 30 through a fifth mask plate 25 (as shown in FIG. 5a), so that an exposed portion 251 and an unexposed portion 252 of the photoresist 250 are formed. After developing, only a pattern of the unexposed portion 252 of the photoresist is left on the position of a pixel area (as shown in FIG. 5b). Next, a pixel electrode is formed through post-baking, etching, and photoresist lifting-off.
It is shown that the conventional technology has a number of steps in the photolithography process, which will inevitably result in some floating particles in the air falling on the substrate and causing deterioration. In addition, equipments such as an exposure device and a development device are expensive, with high operation cost and maintenance cost, thereby manufacturing cost for the array substrate is increased.